CS448 Midterm Exam Topics

The exam is open book and open notes.  Calculators or computers may be used if desired.  You are not allowed to use any network functions on the computer (e.g. searching on Google, messaging).  The topics to be covered are listed below, and will include both qualitative and quantitative questions.

Fundamentals of Computer Design

• Trends in technology
• Cost of producing an IC
• Measuring performance
• Relative execution time, speedup
• CPUTime equation, CPI, IC, Cycle Time
• Normalized, weighted
• Benchmarks
• How benchmarks are selected
• Pitfalls
• Amdahl's law
• MIPS, MFLOPS, and MHZ as benchmarks

MIPS Review

• Be able to read or write a program with basic MIPS instructions, e.g. ADD, BNEZ, LD, SD, etc.

Pipelining

• There is always a pipelining question on the exam!
• Equations for speedup in the ideal case and with stalls
• problems why the speedup equation is not particularly helpful for evaluation
• Five major stages for the simple MIPS architecture
  • IF, ID, EX, MEM, WB
• Pipeline Hazards - Structural, Data, Control
  • What to do when hazards occur (stall)
    • Forwarding for data hazards
  • Types of hazards:  RAW, WAR, WAW
    • Be able to identify each and determine how to address them
  • Role of the compiler in reducing hazards
    • Be able to read/write MIPS code to avoid hazards
    • Scheduling code to avoid hazards
    • Filling in delay slots
• Role of exceptions in the pipeline
  • Stopping, Restarting Code
  • Impact on scheduling of code
• Multiple Cycle Pipelining
  • Unpipelined scheme of multiple functional units
  • Pipelined multiple functional units
  • Problem that arises; now get out of order completion of instructions, new hazards (e.g. WAW, structural)

Instruction Level Parallelism

• Loop Unrolling
  • Why it helps
  • How to unroll a loop and schedule it
  • Eliminating name dependences via different register names in unrolling
  • Finding code we can move around based on control dependences
  • Trick of changing offsets in memory accesses if we move an ADD or SUB earlier in the code sequence
• Dynamic Scheduling
  • Scoreboarding as in CDC 6600
    • There will be a scoreboarding question on the exam!
    • Fill in the Instruction Status window as in the homework problem with the cycle number
    • Limitations (e.g. lack of register renaming)
  • Tomasulo's Algorithm
    • Register renaming idea
    • Reservation stations for each functional unit
    • Common data bus to broadcast results
  • Branch Prediction
    • One, two-bit scheme with finite state automata and Branch History Buffer
    • Correlating predictor that uses history of previous branches
    • Branch target buffer to predict target during IF stage
• Hardware based speculation
  • Separates issue and execution from instruction commit
  • Addition of the Reorder Buffer to Tomasulo's algorithm
    • Role of the ROB and how it allows easy undo of speculated instructions we don't want to commit
    • Role of the ROB and register renaming
  • Handling exceptions
• Limitatations of ILP
  • Amount of parallelism theoretically possible on an ideal machine
  • Limitations imposed by more realistic machine; general affect of:
    • Window size
    • Branch prediction accuracy
    • Number of registers available for renaming
    • Memory alias analysis
  • What types of programs are highly parallelizable vs. more difficult to parallelize

Not on the midterm

• Caching
• Vector machines
• Multiprocessors